In accordance with the increase of the packing density of integrated circuits, the size of a unit cell has been reduced. Accordingly, the size of the gate line of the transistor in such a cell has been reduced, resulting in increased resistance and contact resistance.
In order to solve these problems, a technique has been developed for forming a metal silicide layer on a gate polysilicon electrode, and for forming a metal silicide layer on a contact portion of a silicon substrate. Consequently, the resistance of the gate electrode of the transistor and the contact resistance between the source and drain are reduced, thereby improving the device.
First, the formation of the metal silicide on the gate electrode and the formation of the metal silicide on the source/drain region were carried out as separate processes. However, in order to simplify the process and to reduce formation costs, there was developed a "salicide" technique (self aligned silicide formation technique) in which the gate and source/drain processes were carried out within the same process.
In this salicide method, a metal is coated on both the exposed silicon portion and on the insulator portion, and then a heat treatment is carried out. As a result, a silicidizing reaction occurs on the silicon portion so as to form a silicide, while on the insulator portion the metal remains in a metallic state, which is utilized to selectively form a silicide, and the metal film is selectively removed by an etching process.
When the salicide method was applied to the formation of transistors, it replaced the existing silicide formation method based on the CVD process. Particularly, the process for formation of the transistor includes the process for formation of titanium (Ti) salicide, in which the electrical resistivity of metal and the electrical resistivity of silicide are low.
However, in the conventional Ti salicide process, the silicidizing reaction is achieved through only one round of heat treatment, thereby forming TiSi.sub.2. Therefore, due to the stoichiometry in which one Ti atom requires two Si atoms, the junctions of the source and/or drain of the transistor are severely intruded by TiSi.sub.2. Further, foreign materials intrude into the interface between the TiSi.sub.2 and Al which is used as a wiring layer. Particularly, TiSi.sub.2 is oxidized to form TiO.sub.2, resulting in an increase of the resistance Rc of the contact. Further, the TiSi.sub.2 cannot serve the role of preventing the diffusion of the silicon (Si) atoms and, therefore, the Si atoms pass through the TiSi.sub.2 layer to intrude into the Al wire in a melted state. Accordingly, the problems of Al junction spikes (i.e., Al atoms intruding into the Si substrate to form Al spikes) and the electro-migration of the Al wiring (i.e., electron collisions which can cause movement of metal atoms, thereby causing disconnections in metal lines) remain as before.
In an attempt to overcome the problem of the Si atoms passing through the TiSi.sub.2 into the Al wiring in a melted form, a technique using contact metallization in the form of Al-TiN-TiSi.sub.2 has been developed in which a TiN layer as a diffusion preventing layer is disposed between the Al wiring and the TiSi.sub.2 layer.
This technique, however, results in other problems. That is, the TiN layer has to be separately deposited by way of sputtering. Further, as in the conventional Ti salicide process, when the TiSi.sub.2 layer is exposed to the external atmosphere, foreign materials intrude to oxidize the TiSi.sub.2 layer, thereby forming a natural TiO.sub.2. Consequently, the contact resistance Rc of the interface between TiN and TiSi.sub.2 may not be improved. That is, the diffusion of the Si atoms into the Al wiring can be prevented, but the problem of the intrusion of foreign materials into the junction of TiSi.sub.2 remains as before.
The conventional Ti salicide process will be described referring to FIG. 1.
An active region for forming a unit device and field region 12 for electrically isolating the active regions are formed on p type silicon substrate 11 by applying a LOCOS method. A thermal oxide layer is grown so as to form a gate insulating layer of a transistor, and a polysilicon conductive layer is formed to serve as gate line 13.
A CVD SiO.sub.2 layer is deposited on the opposite side walls of gate line 13, and an etch-back is carried out to form CVD SiO.sub.2 spacer 14. An impurity implantation is carried out, and self-aligned source/drain region 15 is formed between the gate polysilicon layer with gate side wall spacers and the field oxide layer.
Titanium (Ti) is deposited on the whole surface of the wafer by way of sputtering. A heat treatment is carried out at a temperature of 700.degree.-800.degree. C. under an inert gas atmosphere so that TiSi.sub.2 16 may be selectively formed on the surface of the exposed gate line and on the source/drain region of the Si substrate. During the heat treatment, one Ti atom is bonded with two Si atoms to form TiSi.sub.2, and the Si atoms are supplied from the silicon layer or from the polysilicon gate. That is, the metal Ti consumes the exposed silicon in the depthwise direction, thereby forming TiSi.sub.2.
The structure is dipped into an ammonia solution to remove the Ti layer remaining after the silicide reaction. A heat treatment is carried out to stabilize the TiSi.sub.2 layer, and PSG (phospho-silicate glass) layer 17 is formed on the whole surface of the wafer. A contact hole is formed on the source/drain region, and Al is sputtered so as for it to be diffused. A patterning is carried out to form aluminum wiring 18, thereby completing the formation of the transistor.
There is another salicide technique which is disclosed in U.S. Pat. No. 4,855,798. In this technique, Ti is deposited just after the formation of a gate side wall spacer. A heat treatment is carried out so that the Ti upon the insulating layer may become TiN, the Ti on the surface of the silicon layer may become TiSi.sub.2, and a silicide nitride (TiSi.sub.2 N) may be formed on the TiSi.sub.2 layer. After the reaction, the TiN is removed, thereby completing the salicide process. In this technique, the selective etch characteristics of the TiN and the TiSi.sub.2 N are degraded, and therefore a short can occur between the gate and the source/drain region after removing the TiN. The TiSi.sub.2 N layer which remains on the source/drain region after removal of the TiN is too thin to serve as a diffusion preventing layer. Further, the TiSi.sub.2 N layer of the source/drain region after removing the TiN has a stepped shape.
In the above described conventional technique, Ti atoms intrude into the source/drain junction due to the severe consumption of the Si atoms during the formation of the TiSi.sub.2 layer. Therefore, the characteristics of the junction is degraded, and it is impossible to form a thin source/drain junction.
Further, the TiSi.sub.2 layer cannot prevent the diffusion of the Si atoms, and therefore the Si atoms are diffused into the Al wiring. Therefore, the junction is liable to be damaged due to an Al spike, or electro-migration of the Al wiring may occur, thereby deteriorating the reliability of the transistor.
Further, TiSi.sub.2 is easily oxidized upon being exposed to the atmosphere, and therefore when Al has been deposited, foreign materials such as TiO.sub.2 are formed in the interface between the Al layer and the TiSi.sub.2 layer. Consequently, the contact resistance Rc is increased, and therefore the operating speed of the transistor slows.